Video Musings
VESA Media Channel

Following text is extracted from "The Micro Channel Architecture Handbook" Chet Heath and Winn L. Rosch, pages 125-127 Simon & Schuster NY, NY. ISBN 0-13-583493-7 1990. 

   The video extension gives Micro Channel expansion boards direct access to the various inputs of the digital-to-analog convertor or DAC used by VGA. As it's name implies, the DAC makes analog signals compatible with VGA monitors from the digital signals generated by the computer's circuitry. By allowing access to the inputs of the DAC, the Micro Channel video extension allows changes and improvements to be made in the computer's video system without sacrificing monitor compatibility... 

   The video extension (Ed. AVE) uses several important signals. Present here are horizontal and vertical synchronizing signals plus a special control line called ESYNC or enable sync line. This line determines whether the synchronizing signals used in the video system original on the planar board or from an adapter plugged into the Micro Channel. ESYNC is normally held to logical high. Bringing it low enables the system to use the synchronizing signals from the Micro Channel adapter. 
   Video data are transferred across the Micro Channel video extension in digital form using eight video data lines. The data here are used to drive the VGA Digital-to-Analog convertor on the system board. 

Video Extension Signal Descriptions
The following are signal descriptions for the auxiliary and base video extensions of the channel connector. 
VSYNC: Vertical Synchronization: This signal is the vertical synchronization signal to the display. Also see the ESYNC description. 
HSYNC: Horizontal Synchronization: This signal is the horizontal synchronization signal to the display. Also see the ESYNC description. 
BLANK: Blanking Signal: This signal is connected to the BLANK input of the video DAC. When active (0 V dc), this signal tells the DAC to drive its analog color outputs to 0 V dc. Also see the 
ESYNC description. 
P7- P0: Palette Bits: These eight signals contain video information and comprise the PEL address inputs to the video 
DAC. See also the EVIDEO description. 
DCLK: Dot Clock: This signal is the PEL clock used by the DAC to latch the digital video signals, P7 through P0. The signals are latched into the DAC on the rising edge of DCLK. This signal is driven through the EXTCLK input to the VGA when DCLK is driven by the adapter. If an adapter is providing the clock, it must also provide the video data to the DAC. Also see the EDCLK description. 
ESYNC: External Synchronization: This signal is the output-enable signal for the buffer that drives BLANK, VSYNC, and HSYNC. ESYNC is tied to + 5 V dc through a pull-up resistor. When 
ESYNC is high, the VGA drives BLANK, VSYNC, and HSYNC. When ESYNC is pulled low, the adapter drives BLANK, VSYNC, and HSYNC. 
EVIDEO: External Video: This signal is the output-enable signal for the buffer that drives P7 through P0. EVIDEO is tied to + 5 V dc through a pull-up resistor. When EVIDEO is high, the VGA drives P7 through P0. When it is pulled low, the adapter drives P7 through 
EDCLK: External Dot Clock: This signal is the output-enable signal for the buffer that drives DCLK. EDCLK is tied to + 5 V dc through a pull-up resistor. 
   When EDCLK is high, the VGA is the source of DCLK to the DAC and the adapter. The Miscellaneous Output register should not select clock source 2 (010 binary) when EDCLK is high. 
   When EDCLK is pulled low, the adapter drives DCLK. If the adapter is driving the clock, it must also provide the video data to the DAC, and the Miscellaneous Output register must select clock source 2 (010 binary). 

Vesa Media Channel
VMC, like VAFC, offers a 32-bit data path. But VMC supports up to 15 video streams simultaneously and offers a more long-term solution for video computing than VAFC. One developer described VMC as "a video superhighway that bypasses the already-crowded system bus." Since VMC is a dedicated channel for real-time video, peripherals can communicate independently and without slowing the system CPU. VMC decouples the memory subsystem from the video transfer specification, allowing graphics board manufacturers to offer a variety of boards with differing types of graphics memory--DRAM, VRAM (video RAM), synchronous DRAM, RAMBUS, and other future memory standards. 

The VESA Media Channel (VMC) is a dedicated 132 Mbytes-per-second multimedia bus that provides an independent path for the simultaneous processing of several high bandwidth video streams. The VMC directly addresses the current limitations of running video across a computer's system bus. This design solves the universal bandwidth bottleneck and latency issues that exist in all system or processor bus architectures including ISA, EISA, MicroChannel, VL-Bus, and PCI. 

To correct these problems, the VESA Media Channel is designed to allow the transparent integration of video and graphics without the interference of processor interrupts or bus contention. The VESA Media Channel provides the option for a 68-pin multi-drop cable, allowing multiple devices to be combined in a modular fashion. For example, a graphics system supporting the VESA Media Channel can easily and cost-effectively be configured as a capture,  ecode-only, encode-only, or a full encode/decode video system. This is important in applications such as video teleconferencing, and provides flexible cost effective engineering of a particular system. 

     TIP: For any high performance video adapter, make sure that it supports at least the 80-pin VAFC connector or the 68-pin VMC connector. If you see only a 26-pin connector on the card, then the card would not be recommended as that is the standard VFC. Most of the higher-quality multimedia adapters will require a VAFC connection for high-performance video signal transfer. 

VMC Bus pinout HERE
   To move uncompressed video through computer systems and multimedia equipment derived from PC technology in real time, VESA developed a new, high speed bus interface. Called the VESA Media Channel to represent its wide range of applications well beyond traditional PC video systems, the interface was designed with two conflicting goals in mind—high bandwidth and low cost. The result is elegant in its simplicity, carrying few signals beyond video data. 
   VM Channel is designed as a link between multimedia devices within a PC or other equipment. Although it is aimed primarily at expansion boards built under the PCI standard, its transfers are independent of the PCI bus and are not wed to the PCI design at all. Two devices that use the VM Channel can transfer commands and data between themselves without affecting PCI at all. 
   Because it is designed as a supplement to normal expansion buses, the VM Channel depends on a traditional expansion bus to service the basic needs of expansion boards. The VM Channel has no provision for supplying power to the devices linked through it. Nor does it have any provision for addressing memory or input/output ports. 
   VM Channel is a 32-bit bus. The signals it uses are listed in Table 16.11. It is designed to move video data only in 32-bit double-words. The VM Channel also uses the same 32 data lines to send commands throughout the system. Because the VM channel is designed to accommodate devices of limited data handling abilities, such as those with only 8- or 16-bit bus width, all 
commands are limited to an 8-bit width. The channel thus requires one I/O cycle to transfer each command, despite its 8-bit width. When the bus carries these commands, only the lowest bits (on data lines 0 through 7) are significant; the channel devices ignore the upper bits. 

                     Table 16.11. VESA Media Channel Connector Signal Assignments 

Card pin Cable Pin Function   Card pin Cable Pin   Function 
 1          1       -SA          35       2        +EVST(0) 
 2          3       +EVST        36       4         Ground 
 3          5       -BS(0)       37       6        -BS(1) 
 4          7       Ground       38       8        -SNRDY 
 5          9       +Control     39       10        Ground 
 6          11      -Reset       40       12        Ground 
 7          13       Clock       41       14        Ground 
 8          15       Unused      42       16        Ground 
 9          17       +MASK0      43       18        +Mask1 
10          19       Ground      44       20        Data 0 
11          21       Data 1      45       22        Ground 
12          23       Data 2      46       24        Data 3 
13          25       Ground      47       26        Data 4 
14          27       Data 5      48       28        Ground 
15          29       Data 6      49       30        Data 7 
16          31       Ground      50       32        Data 8 
17          33       Data 9      51       34        Ground 
18          35       Data 10     52       36        Data 11 
19          37       Ground      53       38        Data 12 
20          39       Data 13     54       40        Ground 
21          41       Data 14     55       42        Data 15 
22          43       Ground      56       44        Data 16 
23          45       Data 17     57       46        Ground 
24          47       Data 18     58       48        Data 19 
25          49       Ground      59       50        Data 20 
26          51       Data 21     60       52        Ground 
27          53       Data 22     61       54        Data 23 
28          55       Ground      62       56        Data 24 
29          57       Data 25     63       58        Ground 
30          59       Data 26     64       60        Data 27 
31          61       Ground      65       62        Data 28 
32          63       Data 29     66       64        Ground 
33          65       Data 30   67       66        Data 31 
34          67       Ground      68       68        -SB 

The clock of the VMChannel operates as high as 33 MHz, matching the PCI standard. This speed allows the peak throughput of the channel to reach 132MB/sec. 

Data moves through the VM Channel in packets of double-words. Each transfer of one double-word is termed a cycle. The VM Channel design defines two types of cycles, control and data. These are distinguished by the dedicated +Control signal on the bus. When this signal is active during a transfer, it indicates that the next cycle after the transfer is a control cycle. 

Exchanges across the VM Channel are broadcast rather than exchanged. That is, when a source sends out video data, the bus carries the data to all devices connected to the bus. Each device determines whether it should accept and use the data. 

To achieve its high data rate, the VM Channel does not use handshaking between devices or any acknowledgment that the video data was in fact received by its target. The nature of video data underlies this design decision: if real time video doesn’t arrive at its destination at the proper time, it is worthless. Its moment on the screen is lost forever. Re-transmitting old video data would merely be a waste of time and the bus. 

On the other hand, VM Channel uses a not ready signal to indicate that the target to which a device wants to send data is incapable of receiving or processing that data. The not ready signal inhibits the transmission of data from the source device so that unused or superfluous information does not waste bus bandwidth. When a device takes control of the VM Channel then receives a 
not ready indication, control passes from that device to the next one that needs to transfer data across the channel. 

Despite its broadcast design, the VM Channel operates as an arbitrated bus with multiple bus masters. The VMChannel specification allows for up to 15 devices to share data. Several devices may be integrated into a single assembly.  When a device takes control of the VM Channel, the first data it sends out must be a command called the Token Direction, which indicates which device will take command of the bus following the transfer. 

The standard VMChannel connector is an edge connector with the contact fingers spaced on centers measuring 0.05 inches. You’ll find the connector on the top of both ISA and PCI video boards. Figure 16.3 illustrates this connector. 

Figure 16.3 VESA Media Channel card edge connector. 

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